Researchers from POSTECH, SKKU and UESTC have developed air‑stable tin‑based perovskite p‑type transistors using volatile surface reconstruction by treating CsSnI₃ with potassium acetate, removing defect‑forming tin ions and creating a protective KI layer. The devices show top‑level hole mobility and on/off ratio, remain stable in air and at high temperature, and may be used in future memory and display electronics.
Tin (Sn²⁺) halide perovskites are promising lead‑free materials for future electronics because their bandgaps can be tuned and they conduct charge efficiently, but the tin at the surface is easily oxidized in air. Undercoordinated Sn²⁺ sites tend to oxidize to Sn⁴⁺, causing unwanted self‑doping and defects that block charge flow, so conventional tin‑based perovskite transistors can fail within minutes under ambient conditions. In these devices, unreacted tin ions that never fully joined the crystal remain on the surface and act as starting points for oxidation and degradation. To overcome this, the researchers implemented “volatile surface reconstruction”.
They treated the surface of cesium–tin–iodine (CsSnI₃) with potassium acetate (KAc), which encourages the leftover surface tin ions to react into tin acetate (Sn(Ac)₂). Tin acetate is volatile, so it evaporates away when the device is gently heated, effectively stripping out those defect‑forming tin ions. As the authors describe it, “acetate vapor transiently coordinates with undercoordinated Sn sites and volatilizes upon mild annealing.” This process reshapes the surface from a reactive, tin‑rich top layer into a cleaner, more stable interface.
The vacated positions are naturally filled by potassium iodide (KI), which forms during the treatment and builds a thin, self‑protective layer on top of the CsSnI₃. This KI layer acts as a shield between the semiconductor and the outside environment, blocking oxygen and moisture and reducing the number of defect sites. The process removes the problematic tin from the surface and replaces it with a protective coating, suppressing the material’s tendency to self‑dope and keeping the transistor channel closer to its intended, well‑controlled state.
This reconstruction has a strong impact on performance. The treated CsSnI₃ p‑type transistors show robust, stable hole transport, a threshold voltage close to zero and very strong switching behavior, with on/off current ratios exceeding 10⁸. The voltage needed to turn the transistor on decreases, while the hole mobility exceeds 50 cm²/V·s, placing these devices among the highest‑performing p‑type perovskite transistors reported so far. By stabilizing the channel and cutting down defects, the volatile surface reconstruction delivers p‑channel transistors that switch cleanly and efficiently, with low leakage current.
Stability, the main obstacle for tin‑based perovskite electronics, improves dramatically. While conventional devices failed within a few minutes in air, the reconstructed CsSnI₃ transistors operated stably for more than four hours under ambient conditions. More importantly, the authors note that “the reconstructed interface acts as a self‑passivating and thermally resilient barrier, leading to markedly enhanced ambient and thermal stability, with devices maintaining stable operation for over 1 month at 100 °C.” Under accelerated aging at 100 °C, the transistors maintained their initial performance for over a month, showing that the KI‑rich protective layer withstands high temperatures as well as air exposure.
Conceptually, this volatile‑assisted coordination strategy acts like a targeted clean‑up and repair process for a fragile semiconductor surface. Transient acetate molecules “seek out” the most reactive, undercoordinated tin sites and convert them into volatile Sn(Ac)₂ that can be removed, while the subsequent formation of KI at those positions passivates the surface and stabilizes the material’s composition. “These results establish volatile-assisted surface reconstruction as an effective method for defect equilibration in metastable semiconductors, and they provide a general strategy for enabling durable, device-grade functionality in Sn²⁺‑based materials.”
The work tackles a major bottleneck in p‑type transistor technology. Improving the performance of p‑type transistors is particularly challenging, and they have been listed by the Ministry of Science and ICT as one of the “Top 10 future challenges in semiconductors.” When p‑type transistors are fabricated using tin‑based perovskites, holes can flow smoothly, delivering performance comparable to low‑temperature polycrystalline silicon (LTPS) or oxide semiconductors used to drive memory chips and high‑performance displays. Combining that high performance with long‑term stability - mobilities above 50 cm²/V·s, near‑zero threshold voltage, on/off ratios above 10⁸ and month‑scale operation at 100 °C - makes these reconstructed CsSnI₃ devices strong candidates for low‑power logic, advanced display backplanes and densely integrated memory architectures.
Professor Noh said, “We expect this technology to be used as a core element in a wide range of future electronics, including vertically stacked DRAM memory devices for artificial intelligence (AI) computation, next-generation display driver circuits, wearable devices, and highly integrated semiconductor devices.” Because the strategy relies on general chemistry of tin and acetate rather than a single narrow recipe, it offers a blueprint that could be adapted to other Sn‑based perovskites and related semiconductors with similar surface oxidation problems. This positions volatile surface reconstruction as a practical route to bring lead‑free perovskite electronics closer to reliable, device‑grade integration in mainstream products.
